<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR>To see the actual file transmitted to Xilinx, please click <A HREF="./usage_statistics_webtalk.xml">here</A>.<BR><BR><HR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
  <TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>2405991</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Wed Jul 21 14:53:00 2021</TD>
  <TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>Vivado v2018.3 (64-bit)</TD>
  <TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>cf632ab9a35a4fcfaec5d17639ae31c7</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>24</TD>
  <TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>1b6f11acf51455f6a31aadc91a145b6e</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>1b6f11acf51455f6a31aadc91a145b6e</TD>
  <TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>TRUE</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>xc7a100t</TD>
  <TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>artix7</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>fgg484</TD>
  <TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>-1</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>Vivado</TD>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz</TD>
  <TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>3192 MHz</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Microsoft Windows 8 or later , 64-bit</TD>
  <TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release  (build 9200)</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>17.000 GB</TD>
  <TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
<TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>gui_handlers</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>abstractsearchablepanel_show_search=1</TD>
   <TD>addsrcwizard_specify_hdl_netlist_block_design=3</TD>
   <TD>basedialog_apply=43</TD>
   <TD>basedialog_cancel=4</TD>
</TR><TR ALIGN='LEFT'>   <TD>basedialog_ok=187</TD>
   <TD>basedialog_yes=9</TD>
   <TD>cmdmsgdialog_ok=12</TD>
   <TD>cmdmsgdialog_open_messages_view=4</TD>
</TR><TR ALIGN='LEFT'>   <TD>commandsinput_type_tcl_command_here=20</TD>
   <TD>constraintschooserpanel_add_files=1</TD>
   <TD>constraintschooserpanel_create_file=1</TD>
   <TD>coretreetablepanel_core_tree_table=25</TD>
</TR><TR ALIGN='LEFT'>   <TD>createconstraintsfilepanel_file_name=2</TD>
   <TD>createsrcfiledialog_file_name=44</TD>
   <TD>createsrcfiledialog_file_type=1</TD>
   <TD>customizecoredialog_documentation=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>customizecoredialog_ip_location=1</TD>
   <TD>customizeerrordialog_ok=2</TD>
   <TD>filesetpanel_file_set_panel_tree=1810</TD>
   <TD>flownavigatortreepanel_flow_navigator_tree=56</TD>
</TR><TR ALIGN='LEFT'>   <TD>fpgachooser_fpga_table=3</TD>
   <TD>gettingstartedview_create_new_project=1</TD>
   <TD>gettingstartedview_open_project=4</TD>
   <TD>hardwaretreepanel_hardware_tree_table=38</TD>
</TR><TR ALIGN='LEFT'>   <TD>hinputhandler_duplicate_selection=1</TD>
   <TD>hjfilechooserrecentlistpreview_recent_directories=5</TD>
   <TD>hpopuptitle_close=3</TD>
   <TD>labtoolsmenu_jtag_scan_rate=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>launchpanel_dont_show_this_dialog_again=6</TD>
   <TD>logmonitor_monitor=26</TD>
   <TD>mainmenumgr_checkpoint=4</TD>
   <TD>mainmenumgr_edit=24</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainmenumgr_export=4</TD>
   <TD>mainmenumgr_file=12</TD>
   <TD>mainmenumgr_flow=45</TD>
   <TD>mainmenumgr_ip=5</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainmenumgr_project=6</TD>
   <TD>mainmenumgr_reports=44</TD>
   <TD>mainmenumgr_settings=7</TD>
   <TD>mainmenumgr_text_editor=5</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainmenumgr_tools=114</TD>
   <TD>mainmenumgr_view=2</TD>
   <TD>mainmenumgr_window=18</TD>
   <TD>maintoolbarmgr_run=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainwinmenumgr_layout=10</TD>
   <TD>messagewithoptiondialog_dont_show_this_dialog_again=8</TD>
   <TD>msgtreepanel_discard_user_created_messages=3</TD>
   <TD>msgtreepanel_message_severity=16</TD>
</TR><TR ALIGN='LEFT'>   <TD>msgtreepanel_message_view_tree=354</TD>
   <TD>msgview_critical_warnings=2</TD>
   <TD>msgview_warning_messages=14</TD>
   <TD>numjobschooser_number_of_jobs=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_add_sources=46</TD>
   <TD>pacommandnames_auto_connect_target=18</TD>
   <TD>pacommandnames_auto_update_hier=57</TD>
   <TD>pacommandnames_create_hardware_dashboards=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_goto_netlist_design=1</TD>
   <TD>pacommandnames_language_templates=1</TD>
   <TD>pacommandnames_new_project=1</TD>
   <TD>pacommandnames_open_hardware_manager=9</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_open_target=4</TD>
   <TD>pacommandnames_program_fpga=15</TD>
   <TD>pacommandnames_run_bitgen=56</TD>
   <TD>pacommandnames_run_implementation=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_show_product_guide=1</TD>
   <TD>pacommandnames_show_product_webpage=1</TD>
   <TD>pacommandnames_simulation_live_break=6</TD>
   <TD>pacommandnames_simulation_live_run_all=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_simulation_relaunch=29</TD>
   <TD>pacommandnames_simulation_run=6</TD>
   <TD>pacommandnames_simulation_run_behavioral=28</TD>
   <TD>pacommandnames_simulation_settings=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_src_enable=1</TD>
   <TD>pacommandnames_toggle_view_nav=4</TD>
   <TD>paviews_code=45</TD>
   <TD>paviews_device=11</TD>
</TR><TR ALIGN='LEFT'>   <TD>paviews_ip_catalog=1</TD>
   <TD>paviews_project_summary=21</TD>
   <TD>programdebugtab_open_target=2</TD>
   <TD>programdebugtab_program_device=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>programfpgadialog_program=19</TD>
   <TD>progressdialog_background=39</TD>
   <TD>progressdialog_cancel=1</TD>
   <TD>projectnamechooser_choose_project_location=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>projectnamechooser_project_name=1</TD>
   <TD>projectsettingssimulationpanel_select_testbench_top_module=1</TD>
   <TD>rdicommands_copy=1</TD>
   <TD>rdicommands_custom_commands=41</TD>
</TR><TR ALIGN='LEFT'>   <TD>rdicommands_delete=11</TD>
   <TD>rdicommands_properties=3</TD>
   <TD>rdicommands_settings=36</TD>
   <TD>rdicommands_unselect_all=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>rdiviews_waveform_viewer=160</TD>
   <TD>removesourcesdialog_also_delete=5</TD>
   <TD>rungadget_show_warning_and_error_messages_in_messages=1</TD>
   <TD>saveprojectutils_cancel=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>saveprojectutils_save=2</TD>
   <TD>searchcommandcomponent_quick_access=2</TD>
   <TD>selecttopmoduledialog_select_top_module=2</TD>
   <TD>settingsdialog_options_tree=41</TD>
</TR><TR ALIGN='LEFT'>   <TD>settingsdialog_restore=1</TD>
   <TD>settingsrestoredialog_check_all=2</TD>
   <TD>settingsthemepanel_save_as=1</TD>
   <TD>simpleoutputproductdialog_generate_output_products_immediately=19</TD>
</TR><TR ALIGN='LEFT'>   <TD>simulationliverunforcomp_specify_time_and_units=1</TD>
   <TD>simulationobjectspanel_simulation_objects_tree_table=23</TD>
   <TD>simulationscopespanel_simulate_scope_table=165</TD>
   <TD>srcchooserpanel_add_directories=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>srcchooserpanel_add_hdl_and_netlist_files_to_your_project=6</TD>
   <TD>srcchooserpanel_create_file=42</TD>
   <TD>srcchooserpanel_scan_and_add_rtl_include_files_into=1</TD>
   <TD>srcfileproppanels_location=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>srcmenu_ip_documentation=4</TD>
   <TD>srcmenu_ip_hierarchy=45</TD>
   <TD>srcmenu_open_selected_source_files=2</TD>
   <TD>srcmenu_refresh_hierarchy=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>stalerundialog_yes=1</TD>
   <TD>statemonitor_reset_run=1</TD>
   <TD>syntheticagettingstartedview_recent_projects=3</TD>
   <TD>syntheticastatemonitor_cancel=6</TD>
</TR><TR ALIGN='LEFT'>   <TD>taskbanner_close=13</TD>
   <TD>tclconsoleview_tcl_console_code_editor=5</TD>
   <TD>touchpointsurveydialog_no=1</TD>
   <TD>touchpointsurveydialog_yes=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>waveformnametree_waveform_name_tree=36</TD>
   <TD>xpg_coefiledialog_add_row=1</TD>
   <TD>xpg_coefiledialog_close=4</TD>
   <TD>xpg_coefiledialog_current_location_cannot_be_over_written=7</TD>
</TR><TR ALIGN='LEFT'>   <TD>xpg_coefiledialog_delete_row=1</TD>
   <TD>xpg_coefiledialog_help=1</TD>
   <TD>xpg_coefiledialog_save_as=1</TD>
   <TD>xpg_coefiledialog_validate=11</TD>
</TR><TR ALIGN='LEFT'>   <TD>xpg_coefilewidgdet_browse=17</TD>
   <TD>xpg_coefilewidgdet_edit=18</TD>
   <TD>xpg_ipsymbol_show_disabled_ports=11</TD>
</TR>  </TABLE>
  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>java_command_handlers</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>addsources=47</TD>
   <TD>autoconnecttarget=18</TD>
   <TD>coreview=4</TD>
   <TD>createblockdesign=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>customizecore=5</TD>
   <TD>editdelete=12</TD>
   <TD>editpaste=1</TD>
   <TD>editproperties=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>editundo=2</TD>
   <TD>launchprogramfpga=19</TD>
   <TD>newproject=2</TD>
   <TD>openhardwaremanager=14</TD>
</TR><TR ALIGN='LEFT'>   <TD>openproject=4</TD>
   <TD>openrecenttarget=6</TD>
   <TD>opentarget=4</TD>
   <TD>programdevice=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>recustomizecore=35</TD>
   <TD>runbitgen=56</TD>
   <TD>runimplementation=2</TD>
   <TD>runsynthesis=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>savefileproxyhandler=32</TD>
   <TD>showproductguide=1</TD>
   <TD>showproductwebpage=1</TD>
   <TD>showview=30</TD>
</TR><TR ALIGN='LEFT'>   <TD>simulationbreak=6</TD>
   <TD>simulationrelaunch=28</TD>
   <TD>simulationrun=28</TD>
   <TD>simulationrunall=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>toggleviewnavigator=4</TD>
   <TD>toolssettings=39</TD>
   <TD>toolstemplates=2</TD>
   <TD>unselectallcmdhandler=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>viewtaskimplementation=1</TD>
   <TD>viewtaskrtlanalysis=2</TD>
   <TD>waveformsaveconfiguration=4</TD>
</TR>  </TABLE>
</TR><TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>other_data</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>guimode=24</TD>
</TR>  </TABLE>
  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>project_data</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>constraintsetcount=1</TD>
   <TD>core_container=false</TD>
   <TD>currentimplrun=impl_1</TD>
   <TD>currentsynthesisrun=synth_1</TD>
</TR><TR ALIGN='LEFT'>   <TD>default_library=xil_defaultlib</TD>
   <TD>designmode=RTL</TD>
   <TD>export_simulation_activehdl=21</TD>
   <TD>export_simulation_ies=21</TD>
</TR><TR ALIGN='LEFT'>   <TD>export_simulation_modelsim=21</TD>
   <TD>export_simulation_questa=21</TD>
   <TD>export_simulation_riviera=21</TD>
   <TD>export_simulation_vcs=21</TD>
</TR><TR ALIGN='LEFT'>   <TD>export_simulation_xsim=21</TD>
   <TD>implstrategy=Vivado Implementation Defaults</TD>
   <TD>launch_simulation_activehdl=0</TD>
   <TD>launch_simulation_ies=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_modelsim=0</TD>
   <TD>launch_simulation_questa=0</TD>
   <TD>launch_simulation_riviera=0</TD>
   <TD>launch_simulation_vcs=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_xsim=108</TD>
   <TD>simulator_language=Mixed</TD>
   <TD>srcsetcount=33</TD>
   <TD>synthesisstrategy=Vivado Synthesis Defaults</TD>
</TR><TR ALIGN='LEFT'>   <TD>target_language=Verilog</TD>
   <TD>target_simulator=XSim</TD>
   <TD>totalimplruns=3</TD>
   <TD>totalsynthesisruns=3</TD>
</TR>  </TABLE>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>unisim_transformation</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>post_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufg=3</TD>
    <TD>carry4=66</TD>
    <TD>fdce=1618</TD>
    <TD>fdpe=9</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdre=92</TD>
    <TD>gnd=13</TD>
    <TD>ibuf=26</TD>
    <TD>ldce=45</TD>
</TR><TR ALIGN='LEFT'>    <TD>ldpe=1</TD>
    <TD>lut1=25</TD>
    <TD>lut2=301</TD>
    <TD>lut3=130</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut4=315</TD>
    <TD>lut5=293</TD>
    <TD>lut6=1619</TD>
    <TD>muxf7=4629</TD>
</TR><TR ALIGN='LEFT'>    <TD>muxf8=2272</TD>
    <TD>obuf=40</TD>
    <TD>plle2_adv=1</TD>
    <TD>rams64e=8192</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcc=14</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>pre_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufg=3</TD>
    <TD>carry4=66</TD>
    <TD>fdce=1618</TD>
    <TD>fdpe=9</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdre=92</TD>
    <TD>gnd=13</TD>
    <TD>ibuf=27</TD>
    <TD>ldce=45</TD>
</TR><TR ALIGN='LEFT'>    <TD>ldpe=1</TD>
    <TD>lut1=25</TD>
    <TD>lut2=301</TD>
    <TD>lut3=130</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut4=315</TD>
    <TD>lut5=293</TD>
    <TD>lut6=1619</TD>
    <TD>muxf7=533</TD>
</TR><TR ALIGN='LEFT'>    <TD>muxf8=224</TD>
    <TD>obuf=40</TD>
    <TD>plle2_adv=1</TD>
    <TD>ram256x1s=2048</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcc=14</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>ip_statistics</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clk_wiz_v6_0_2_0_0/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>clkin1_period=10.000</TD>
    <TD>clkin2_period=10.000</TD>
    <TD>clock_mgr_type=NA</TD>
    <TD>component_name=cpuclk</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>enable_axi=0</TD>
    <TD>feedback_source=FDBK_AUTO</TD>
    <TD>feedback_type=SINGLE</TD>
</TR><TR ALIGN='LEFT'>    <TD>iptotal=1</TD>
    <TD>manual_override=false</TD>
    <TD>num_out_clk=1</TD>
    <TD>primitive=PLL</TD>
</TR><TR ALIGN='LEFT'>    <TD>use_dyn_phase_shift=false</TD>
    <TD>use_dyn_reconfig=false</TD>
    <TD>use_inclk_stopped=false</TD>
    <TD>use_inclk_switchover=false</TD>
</TR><TR ALIGN='LEFT'>    <TD>use_locked=false</TD>
    <TD>use_max_i_jitter=false</TD>
    <TD>use_min_o_jitter=false</TD>
    <TD>use_phase_alignment=true</TD>
</TR><TR ALIGN='LEFT'>    <TD>use_power_down=false</TD>
    <TD>use_reset=false</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>dist_mem_gen_v8_0_12/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_addr_width=14</TD>
    <TD>c_default_data=0</TD>
    <TD>c_depth=16384</TD>
    <TD>c_elaboration_dir=./</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_family=artix7</TD>
    <TD>c_has_clk=1</TD>
    <TD>c_has_d=1</TD>
    <TD>c_has_dpo=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_dpra=0</TD>
    <TD>c_has_i_ce=0</TD>
    <TD>c_has_qdpo=0</TD>
    <TD>c_has_qdpo_ce=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_qdpo_clk=0</TD>
    <TD>c_has_qdpo_rst=0</TD>
    <TD>c_has_qdpo_srst=0</TD>
    <TD>c_has_qspo=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_qspo_ce=0</TD>
    <TD>c_has_qspo_rst=0</TD>
    <TD>c_has_qspo_srst=0</TD>
    <TD>c_has_spo=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_we=1</TD>
    <TD>c_mem_init_file=no_coe_file_loaded</TD>
    <TD>c_mem_type=1</TD>
    <TD>c_parser_type=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_pipeline_stages=0</TD>
    <TD>c_qce_joined=0</TD>
    <TD>c_qualify_we=0</TD>
    <TD>c_read_mif=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_reg_a_d_inputs=0</TD>
    <TD>c_reg_dpra_input=0</TD>
    <TD>c_sync_enable=1</TD>
    <TD>c_width=32</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=false</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=12</TD>
    <TD>x_iplanguage=VERILOG</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=dist_mem_gen</TD>
    <TD>x_ipproduct=Vivado 2018.3</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=8.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>dist_mem_gen_v8_0_12/2</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_addr_width=14</TD>
    <TD>c_default_data=0</TD>
    <TD>c_depth=16384</TD>
    <TD>c_elaboration_dir=./</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_family=artix7</TD>
    <TD>c_has_clk=0</TD>
    <TD>c_has_d=0</TD>
    <TD>c_has_dpo=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_dpra=0</TD>
    <TD>c_has_i_ce=0</TD>
    <TD>c_has_qdpo=0</TD>
    <TD>c_has_qdpo_ce=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_qdpo_clk=0</TD>
    <TD>c_has_qdpo_rst=0</TD>
    <TD>c_has_qdpo_srst=0</TD>
    <TD>c_has_qspo=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_qspo_ce=0</TD>
    <TD>c_has_qspo_rst=0</TD>
    <TD>c_has_qspo_srst=0</TD>
    <TD>c_has_spo=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_we=0</TD>
    <TD>c_mem_init_file=[user-defined]</TD>
    <TD>c_mem_type=0</TD>
    <TD>c_parser_type=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_pipeline_stages=0</TD>
    <TD>c_qce_joined=0</TD>
    <TD>c_qualify_we=0</TD>
    <TD>c_read_mif=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_reg_a_d_inputs=0</TD>
    <TD>c_reg_dpra_input=0</TD>
    <TD>c_sync_enable=1</TD>
    <TD>c_width=32</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=false</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=12</TD>
    <TD>x_iplanguage=VERILOG</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=dist_mem_gen</TD>
    <TD>x_ipproduct=Vivado 2018.3</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=8.0</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_drc</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-append=default::[not_specified]</TD>
    <TD>-checks=default::[not_specified]</TD>
    <TD>-fail_on=default::[not_specified]</TD>
    <TD>-force=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-format=default::[not_specified]</TD>
    <TD>-internal=default::[not_specified]</TD>
    <TD>-internal_only=default::[not_specified]</TD>
    <TD>-messages=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-name=default::[not_specified]</TD>
    <TD>-no_waivers=default::[not_specified]</TD>
    <TD>-return_string=default::[not_specified]</TD>
    <TD>-ruledecks=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-upgrade_cw=default::[not_specified]</TD>
    <TD>-waived=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>cfgbvs-1=1</TD>
    <TD>pdrc-153=10</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_methodology</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-append=default::[not_specified]</TD>
    <TD>-checks=default::[not_specified]</TD>
    <TD>-fail_on=default::[not_specified]</TD>
    <TD>-force=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-format=default::[not_specified]</TD>
    <TD>-messages=default::[not_specified]</TD>
    <TD>-name=default::[not_specified]</TD>
    <TD>-return_string=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-slack_lesser_than=default::[not_specified]</TD>
    <TD>-waived=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>ckld-2=1</TD>
    <TD>lutar-1=10</TD>
    <TD>timing-16=681</TD>
    <TD>timing-17=46</TD>
</TR><TR ALIGN='LEFT'>    <TD>timing-20=46</TD>
    <TD>timing-27=1</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_power</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-advisory=default::[not_specified]</TD>
    <TD>-append=default::[not_specified]</TD>
    <TD>-file=[specified]</TD>
    <TD>-format=default::text</TD>
</TR><TR ALIGN='LEFT'>    <TD>-hier=default::power</TD>
    <TD>-hierarchical_depth=default::4</TD>
    <TD>-l=default::[not_specified]</TD>
    <TD>-name=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-no_propagation=default::[not_specified]</TD>
    <TD>-return_string=default::[not_specified]</TD>
    <TD>-rpx=[specified]</TD>
    <TD>-verbose=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-vid=default::[not_specified]</TD>
    <TD>-xpe=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>airflow=250 (LFM)</TD>
    <TD>ambient_temp=25.0 (C)</TD>
    <TD>bi-dir_toggle=12.500000</TD>
    <TD>bidir_output_enable=1.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>board_layers=12to15 (12 to 15 Layers)</TD>
    <TD>board_selection=medium (10&quot;x10&quot;)</TD>
    <TD>clocks=0.015219</TD>
    <TD>confidence_level_clock_activity=High</TD>
</TR><TR ALIGN='LEFT'>    <TD>confidence_level_design_state=High</TD>
    <TD>confidence_level_device_models=High</TD>
    <TD>confidence_level_internal_activity=Medium</TD>
    <TD>confidence_level_io_activity=Low</TD>
</TR><TR ALIGN='LEFT'>    <TD>confidence_level_overall=Low</TD>
    <TD>customer=TBD</TD>
    <TD>customer_class=TBD</TD>
    <TD>devstatic=0.097245</TD>
</TR><TR ALIGN='LEFT'>    <TD>die=xc7a100tfgg484-1</TD>
    <TD>dsp_output_toggle=12.500000</TD>
    <TD>dynamic=0.132400</TD>
    <TD>effective_thetaja=2.7</TD>
</TR><TR ALIGN='LEFT'>    <TD>enable_probability=0.990000</TD>
    <TD>family=artix7</TD>
    <TD>ff_toggle=12.500000</TD>
    <TD>flow_state=routed</TD>
</TR><TR ALIGN='LEFT'>    <TD>heatsink=medium (Medium Profile)</TD>
    <TD>i/o=0.011702</TD>
    <TD>input_toggle=12.500000</TD>
    <TD>junction_temp=25.6 (C)</TD>
</TR><TR ALIGN='LEFT'>    <TD>logic=0.001546</TD>
    <TD>mgtavcc_dynamic_current=0.000000</TD>
    <TD>mgtavcc_static_current=0.000000</TD>
    <TD>mgtavcc_total_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>mgtavcc_voltage=1.000000</TD>
    <TD>mgtavtt_dynamic_current=0.000000</TD>
    <TD>mgtavtt_static_current=0.000000</TD>
    <TD>mgtavtt_total_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>mgtavtt_voltage=1.200000</TD>
    <TD>netlist_net_matched=NA</TD>
    <TD>off-chip_power=0.000000</TD>
    <TD>on-chip_power=0.229645</TD>
</TR><TR ALIGN='LEFT'>    <TD>output_enable=1.000000</TD>
    <TD>output_load=5.000000</TD>
    <TD>output_toggle=12.500000</TD>
    <TD>package=fgg484</TD>
</TR><TR ALIGN='LEFT'>    <TD>pct_clock_constrained=7.000000</TD>
    <TD>pct_inputs_defined=3</TD>
    <TD>platform=nt64</TD>
    <TD>pll=0.100979</TD>
</TR><TR ALIGN='LEFT'>    <TD>process=typical</TD>
    <TD>ram_enable=50.000000</TD>
    <TD>ram_write=50.000000</TD>
    <TD>read_saif=False</TD>
</TR><TR ALIGN='LEFT'>    <TD>set/reset_probability=0.000000</TD>
    <TD>signal_rate=False</TD>
    <TD>signals=0.002954</TD>
    <TD>simulation_file=None</TD>
</TR><TR ALIGN='LEFT'>    <TD>speedgrade=-1</TD>
    <TD>static_prob=False</TD>
    <TD>temp_grade=commercial</TD>
    <TD>thetajb=6.8 (C/W)</TD>
</TR><TR ALIGN='LEFT'>    <TD>thetasa=4.6 (C/W)</TD>
    <TD>toggle_rate=False</TD>
    <TD>user_board_temp=25.0 (C)</TD>
    <TD>user_effective_thetaja=2.7</TD>
</TR><TR ALIGN='LEFT'>    <TD>user_junc_temp=25.6 (C)</TD>
    <TD>user_thetajb=6.8 (C/W)</TD>
    <TD>user_thetasa=4.6 (C/W)</TD>
    <TD>vccadc_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccadc_static_current=0.020000</TD>
    <TD>vccadc_total_current=0.020000</TD>
    <TD>vccadc_voltage=1.800000</TD>
    <TD>vccaux_dynamic_current=0.051298</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccaux_io_dynamic_current=0.000000</TD>
    <TD>vccaux_io_static_current=0.000000</TD>
    <TD>vccaux_io_total_current=0.000000</TD>
    <TD>vccaux_io_voltage=1.800000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccaux_static_current=0.018152</TD>
    <TD>vccaux_total_current=0.069449</TD>
    <TD>vccaux_voltage=1.800000</TD>
    <TD>vccbram_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccbram_static_current=0.000247</TD>
    <TD>vccbram_total_current=0.000247</TD>
    <TD>vccbram_voltage=1.000000</TD>
    <TD>vccint_dynamic_current=0.029265</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccint_static_current=0.015125</TD>
    <TD>vccint_total_current=0.044390</TD>
    <TD>vccint_voltage=1.000000</TD>
    <TD>vcco12_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco12_static_current=0.000000</TD>
    <TD>vcco12_total_current=0.000000</TD>
    <TD>vcco12_voltage=1.200000</TD>
    <TD>vcco135_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco135_static_current=0.000000</TD>
    <TD>vcco135_total_current=0.000000</TD>
    <TD>vcco135_voltage=1.350000</TD>
    <TD>vcco15_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco15_static_current=0.000000</TD>
    <TD>vcco15_total_current=0.000000</TD>
    <TD>vcco15_voltage=1.500000</TD>
    <TD>vcco18_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco18_static_current=0.000000</TD>
    <TD>vcco18_total_current=0.000000</TD>
    <TD>vcco18_voltage=1.800000</TD>
    <TD>vcco25_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco25_static_current=0.000000</TD>
    <TD>vcco25_total_current=0.000000</TD>
    <TD>vcco25_voltage=2.500000</TD>
    <TD>vcco33_dynamic_current=0.003272</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco33_static_current=0.004000</TD>
    <TD>vcco33_total_current=0.007272</TD>
    <TD>vcco33_voltage=3.300000</TD>
    <TD>version=2018.3</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_utilization</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clocking</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufgctrl_available=32</TD>
    <TD>bufgctrl_fixed=0</TD>
    <TD>bufgctrl_used=3</TD>
    <TD>bufgctrl_util_percentage=9.38</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufhce_available=96</TD>
    <TD>bufhce_fixed=0</TD>
    <TD>bufhce_used=0</TD>
    <TD>bufhce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufio_available=24</TD>
    <TD>bufio_fixed=0</TD>
    <TD>bufio_used=0</TD>
    <TD>bufio_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufmrce_available=12</TD>
    <TD>bufmrce_fixed=0</TD>
    <TD>bufmrce_used=0</TD>
    <TD>bufmrce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufr_available=24</TD>
    <TD>bufr_fixed=0</TD>
    <TD>bufr_used=0</TD>
    <TD>bufr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>mmcme2_adv_available=6</TD>
    <TD>mmcme2_adv_fixed=0</TD>
    <TD>mmcme2_adv_used=0</TD>
    <TD>mmcme2_adv_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>plle2_adv_available=6</TD>
    <TD>plle2_adv_fixed=0</TD>
    <TD>plle2_adv_used=1</TD>
    <TD>plle2_adv_util_percentage=16.67</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>dsp</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>dsps_available=240</TD>
    <TD>dsps_fixed=0</TD>
    <TD>dsps_used=0</TD>
    <TD>dsps_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>io_standard</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>blvds_25=0</TD>
    <TD>diff_hstl_i=0</TD>
    <TD>diff_hstl_i_18=0</TD>
    <TD>diff_hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_hstl_ii_18=0</TD>
    <TD>diff_hsul_12=0</TD>
    <TD>diff_mobile_ddr=0</TD>
    <TD>diff_sstl135=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl135_r=0</TD>
    <TD>diff_sstl15=0</TD>
    <TD>diff_sstl15_r=0</TD>
    <TD>diff_sstl18_i=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl18_ii=0</TD>
    <TD>hstl_i=0</TD>
    <TD>hstl_i_18=0</TD>
    <TD>hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>hstl_ii_18=0</TD>
    <TD>hsul_12=0</TD>
    <TD>lvcmos12=0</TD>
    <TD>lvcmos15=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lvcmos18=0</TD>
    <TD>lvcmos25=0</TD>
    <TD>lvcmos33=1</TD>
    <TD>lvds_25=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lvttl=0</TD>
    <TD>mini_lvds_25=0</TD>
    <TD>mobile_ddr=0</TD>
    <TD>pci33_3=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>ppds_25=0</TD>
    <TD>rsds_25=0</TD>
    <TD>sstl135=0</TD>
    <TD>sstl135_r=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>sstl15=0</TD>
    <TD>sstl15_r=0</TD>
    <TD>sstl18_i=0</TD>
    <TD>sstl18_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>tmds_33=0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>memory</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>block_ram_tile_available=135</TD>
    <TD>block_ram_tile_fixed=0</TD>
    <TD>block_ram_tile_used=0</TD>
    <TD>block_ram_tile_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb18_available=270</TD>
    <TD>ramb18_fixed=0</TD>
    <TD>ramb18_used=0</TD>
    <TD>ramb18_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb36_fifo_available=135</TD>
    <TD>ramb36_fifo_fixed=0</TD>
    <TD>ramb36_fifo_used=0</TD>
    <TD>ramb36_fifo_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>primitives</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufg_functional_category=Clock</TD>
    <TD>bufg_used=3</TD>
    <TD>carry4_functional_category=CarryLogic</TD>
    <TD>carry4_used=66</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdce_functional_category=Flop &amp; Latch</TD>
    <TD>fdce_used=1618</TD>
    <TD>fdpe_functional_category=Flop &amp; Latch</TD>
    <TD>fdpe_used=9</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdre_functional_category=Flop &amp; Latch</TD>
    <TD>fdre_used=60</TD>
    <TD>ibuf_functional_category=IO</TD>
    <TD>ibuf_used=26</TD>
</TR><TR ALIGN='LEFT'>    <TD>ldce_functional_category=Flop &amp; Latch</TD>
    <TD>ldce_used=45</TD>
    <TD>ldpe_functional_category=Flop &amp; Latch</TD>
    <TD>ldpe_used=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut1_functional_category=LUT</TD>
    <TD>lut1_used=5</TD>
    <TD>lut2_functional_category=LUT</TD>
    <TD>lut2_used=301</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut3_functional_category=LUT</TD>
    <TD>lut3_used=130</TD>
    <TD>lut4_functional_category=LUT</TD>
    <TD>lut4_used=315</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut5_functional_category=LUT</TD>
    <TD>lut5_used=293</TD>
    <TD>lut6_functional_category=LUT</TD>
    <TD>lut6_used=1619</TD>
</TR><TR ALIGN='LEFT'>    <TD>muxf7_functional_category=MuxFx</TD>
    <TD>muxf7_used=4629</TD>
    <TD>muxf8_functional_category=MuxFx</TD>
    <TD>muxf8_used=2272</TD>
</TR><TR ALIGN='LEFT'>    <TD>obuf_functional_category=IO</TD>
    <TD>obuf_used=40</TD>
    <TD>plle2_adv_functional_category=Clock</TD>
    <TD>plle2_adv_used=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>rams64e_functional_category=Distributed Memory</TD>
    <TD>rams64e_used=8192</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>slice_logic</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>f7_muxes_available=31700</TD>
    <TD>f7_muxes_fixed=0</TD>
    <TD>f7_muxes_used=4629</TD>
    <TD>f7_muxes_util_percentage=14.60</TD>
</TR><TR ALIGN='LEFT'>    <TD>f8_muxes_available=15850</TD>
    <TD>f8_muxes_fixed=0</TD>
    <TD>f8_muxes_used=2272</TD>
    <TD>f8_muxes_util_percentage=14.33</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_distributed_ram_fixed=0</TD>
    <TD>lut_as_distributed_ram_used=8192</TD>
    <TD>lut_as_logic_available=63400</TD>
    <TD>lut_as_logic_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_used=2431</TD>
    <TD>lut_as_logic_util_percentage=3.83</TD>
    <TD>lut_as_memory_available=19000</TD>
    <TD>lut_as_memory_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_used=8192</TD>
    <TD>lut_as_memory_util_percentage=43.12</TD>
    <TD>lut_as_shift_register_fixed=0</TD>
    <TD>lut_as_shift_register_used=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_flip_flop_available=126800</TD>
    <TD>register_as_flip_flop_fixed=0</TD>
    <TD>register_as_flip_flop_used=1687</TD>
    <TD>register_as_flip_flop_util_percentage=1.33</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_latch_available=126800</TD>
    <TD>register_as_latch_fixed=0</TD>
    <TD>register_as_latch_used=46</TD>
    <TD>register_as_latch_util_percentage=0.04</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_luts_available=63400</TD>
    <TD>slice_luts_fixed=0</TD>
    <TD>slice_luts_used=10623</TD>
    <TD>slice_luts_util_percentage=16.76</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_available=126800</TD>
    <TD>slice_registers_fixed=0</TD>
    <TD>slice_registers_used=1733</TD>
    <TD>slice_registers_util_percentage=1.37</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_distributed_ram_fixed=0</TD>
    <TD>lut_as_distributed_ram_used=8192</TD>
    <TD>lut_as_logic_available=63400</TD>
    <TD>lut_as_logic_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_used=2431</TD>
    <TD>lut_as_logic_util_percentage=3.83</TD>
    <TD>lut_as_memory_available=19000</TD>
    <TD>lut_as_memory_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_used=8192</TD>
    <TD>lut_as_memory_util_percentage=43.12</TD>
    <TD>lut_as_shift_register_fixed=0</TD>
    <TD>lut_as_shift_register_used=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_in_front_of_the_register_is_unused_fixed=0</TD>
    <TD>lut_in_front_of_the_register_is_unused_used=912</TD>
    <TD>lut_in_front_of_the_register_is_used_fixed=912</TD>
    <TD>lut_in_front_of_the_register_is_used_used=398</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_driven_from_outside_the_slice_fixed=398</TD>
    <TD>register_driven_from_outside_the_slice_used=1310</TD>
    <TD>register_driven_from_within_the_slice_fixed=1310</TD>
    <TD>register_driven_from_within_the_slice_used=423</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_available=15850</TD>
    <TD>slice_fixed=0</TD>
    <TD>slice_registers_available=126800</TD>
    <TD>slice_registers_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_used=1733</TD>
    <TD>slice_registers_util_percentage=1.37</TD>
    <TD>slice_used=3090</TD>
    <TD>slice_util_percentage=19.50</TD>
</TR><TR ALIGN='LEFT'>    <TD>slicel_fixed=0</TD>
    <TD>slicel_used=1005</TD>
    <TD>slicem_fixed=0</TD>
    <TD>slicem_used=2085</TD>
</TR><TR ALIGN='LEFT'>    <TD>unique_control_sets_available=15850</TD>
    <TD>unique_control_sets_fixed=15850</TD>
    <TD>unique_control_sets_used=115</TD>
    <TD>unique_control_sets_util_percentage=0.73</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o5_and_o6_fixed=0.73</TD>
    <TD>using_o5_and_o6_used=0</TD>
    <TD>using_o5_output_only_fixed=0</TD>
    <TD>using_o5_output_only_used=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o6_output_only_fixed=0</TD>
    <TD>using_o6_output_only_used=8192</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>specific_feature</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bscane2_available=4</TD>
    <TD>bscane2_fixed=0</TD>
    <TD>bscane2_used=0</TD>
    <TD>bscane2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>capturee2_available=1</TD>
    <TD>capturee2_fixed=0</TD>
    <TD>capturee2_used=0</TD>
    <TD>capturee2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>dna_port_available=1</TD>
    <TD>dna_port_fixed=0</TD>
    <TD>dna_port_used=0</TD>
    <TD>dna_port_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>efuse_usr_available=1</TD>
    <TD>efuse_usr_fixed=0</TD>
    <TD>efuse_usr_used=0</TD>
    <TD>efuse_usr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>frame_ecce2_available=1</TD>
    <TD>frame_ecce2_fixed=0</TD>
    <TD>frame_ecce2_used=0</TD>
    <TD>frame_ecce2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>icape2_available=2</TD>
    <TD>icape2_fixed=0</TD>
    <TD>icape2_used=0</TD>
    <TD>icape2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcie_2_1_available=1</TD>
    <TD>pcie_2_1_fixed=0</TD>
    <TD>pcie_2_1_used=0</TD>
    <TD>pcie_2_1_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>startupe2_available=1</TD>
    <TD>startupe2_fixed=0</TD>
    <TD>startupe2_used=0</TD>
    <TD>startupe2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>xadc_available=1</TD>
    <TD>xadc_fixed=0</TD>
    <TD>xadc_used=0</TD>
    <TD>xadc_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>synthesis</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-assert=default::[not_specified]</TD>
    <TD>-bufg=default::12</TD>
    <TD>-cascade_dsp=default::auto</TD>
    <TD>-constrset=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-control_set_opt_threshold=default::auto</TD>
    <TD>-directive=default::default</TD>
    <TD>-fanout_limit=default::10000</TD>
    <TD>-flatten_hierarchy=default::rebuilt</TD>
</TR><TR ALIGN='LEFT'>    <TD>-fsm_extraction=default::auto</TD>
    <TD>-gated_clock_conversion=default::off</TD>
    <TD>-generic=default::[not_specified]</TD>
    <TD>-include_dirs=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-keep_equivalent_registers=default::[not_specified]</TD>
    <TD>-max_bram=default::-1</TD>
    <TD>-max_bram_cascade_height=default::-1</TD>
    <TD>-max_dsp=default::-1</TD>
</TR><TR ALIGN='LEFT'>    <TD>-max_uram=default::-1</TD>
    <TD>-max_uram_cascade_height=default::-1</TD>
    <TD>-mode=default::default</TD>
    <TD>-name=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-no_lc=default::[not_specified]</TD>
    <TD>-no_srlextract=default::[not_specified]</TD>
    <TD>-no_timing_driven=default::[not_specified]</TD>
    <TD>-part=xc7a100tfgg484-1</TD>
</TR><TR ALIGN='LEFT'>    <TD>-resource_sharing=default::auto</TD>
    <TD>-retiming=default::[not_specified]</TD>
    <TD>-rtl=default::[not_specified]</TD>
    <TD>-rtl_skip_constraints=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-rtl_skip_ip=default::[not_specified]</TD>
    <TD>-seu_protect=default::none</TD>
    <TD>-sfcu=default::[not_specified]</TD>
    <TD>-shreg_min_size=default::3</TD>
</TR><TR ALIGN='LEFT'>    <TD>-top=top</TD>
    <TD>-verilog_define=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>elapsed=00:00:34s</TD>
    <TD>hls_ip=0</TD>
    <TD>memory_gain=605.273MB</TD>
    <TD>memory_peak=887.813MB</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>xsim</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-sim_mode=default::behavioral</TD>
    <TD>-sim_type=default::</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
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